Speech compressor-expander

ABSTRACT

An improved speech compressor provides frequency transformation by passing speech signals through an analog shift register and controlling the shift rate of the register with a linearly varying periodicity with noise cancellation of the characteristic noise in the shift registers and the control of the sample period and output blanking to improve the signal output characteristic and minimize noise components therein. The system provides a single compression-expansion manual control which varies the record reproducer transport speed and the rate of change of the linearly varying pulse periodicity to provide a unitary control for selecting the corresponding compression ratio and automatically modifies the sample period to optimize the signal and discard intervals as the selected compression or expansion ratio is changed.

United States Patent [191 Schif fman SPEECH COMPRESSOR-EXPANDER Murray M. Schifiman, Westport, Conn.

[75] Inventor:

Filed: Feb. 12, 1973 Appl. N0.: 331,550

Related US. Application Data Continuation-impart of Ser. No. 171,571, Aug. 13, 1971, Pat. No. 3,786,195.

[52] US. Cl. 360/25, 179/15.55 T, 360/8,

360/73 Int. CL. Gllb 15/46, Gl lb 15/18, G1 lb 19/28 Field of Search 179/100.2 B, 100.2 S, 100.2 R,

179/1002 X, 100.1 S, 15.55 TC; 17816.6 TC

References Cited UNITED STATES PATENTS Blaney 179/1002 R Hodder 179/100.2 R Hurst et a1 178/66 TC Greefkes 179/100.1 S Greenberg et a1. 179/1002 B VARIABLE I [45] Aug. 6, 1974 3,621,150 11/1971 Pappas ..179/100.2B

3,681,523 8/1972 Sidline 179/1002 B OTHER PUBLICATlONS Lee, Time Compression and Expansion of Speech by the Sampling Method, Nov. 1972, Journal of the Audio Engineering Society, Vol. 20, No. 9, pages 738-742.

Primary Examiner-Alfred H. Eddleman Attorney, Agent, or Firm-Chittick, Thompson & Pfund [57] ABSTRACT An improved speech compressor provides frequency transformation by passing speech signals through an analog shift register and controlling the shift rate of the register with a linearly varying periodicity with noise cancellation of the characteristicrnoise in the shift registers and the control of the sample period and output blanking to improve the signal output characteristic and minimize noise components therein. The

system provides a single compression-expansion manual control which varies the record reproducer transport speed and the rate of change of the linearly varying pulse periodicity to provide a unitary control for selecting the corresponding compression ratio and automatically modifies the sample period to optimize the signal and discard intervals as the selected compression or expansion ratio is changed. I

15 Claims, 8 Drawing Figures VOLUME CONTROL SPEED MOTOR 22 23 2s 1 3| 32 l PRE AMP rasouencv AMP COMPRESSED EQUALIZER PROCESSOR SPEACH CONTROL 1 24-- CIRCUIT ee 1 I i 33 i 29 TONE CONTROL PA'IENIEB SIIIII 3.828.361

SHEET 1 OF 2 I VOLUME CONTROL l2 II 2| 22 23 25 3| 32 :E% PLAYBACK PRE AMP FREQUENCY AMP COMPRESSED MOTOR HEAD EQUALIZER PROCESSOR SPEACH CONTROL I I4 24 CIRCUIT I 26 I I E JQMAUQ jfifli 29 TONE ""5" I CONTROL 72 I4 256 /68 AUDIO IN V STAGE s 69 FIG. 2 I STAGE 73 J1 I 54 I f rl ;n I

42 VOLTAGE AUDIO AMP I 46 CONTROLLED I I AND ZERO- I AUDIO Iv R MP v PERIOD I n CROSSING o r \f(c) GENERATOR GENERATOR DRIVERS DETECTOR I FIG.4A wow I (GAIN=I) I 25 44 I I 53 FIG.2A I I 52 l; I To I R/ESET I u E 7? /I mo TeoR I RAMPTO 48\ 50 I \Sl SHOT I V or 7.8V I I l I RAMP I M 17 I 43\ BLANK I ENDED- I83 2:550-

47\ V ENABLE RESET BLANK CR SSING EC AND AUTO I J'\ D FF I P LSES RESET I I a! R \76I I a2 l I COUNTER CHIP I IH H 2 z s v FIG. 2A P PAIENIEIJIUB 61914 aaaassi FORCES I BLANK FIG. 3C nnnuunm FIG. 4A

47 93 52 VEC l1 RESE T will saa R ALWAYS RESET E 4B COMPRESSION VOLTS VEC RESET Z.C. LEVEL FIG. 4c 1 ERIE-VECI VOLTS z.c. RESET REGION VEC 5.0

EXPANSION TmIn.-- APPROXIMATELY CONSTANT PERIOD IN EXPANSION 1 SPEECH COMPRESSOR-EXPANDER CROSS REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of applicants copending application Ser. No. 171,571, filed Aug. 13, 1971, now US. Pat. No. 3,786,195, the disclosure of which is hereby incorporated by reference. Applicants applications filed of even date herewith entitled SYSTEM FOR NULLIFYING SIGNAL PRO- CESSOR DISTORTIONS, Ser. No. 331,576 and SYS- TEM FOR GENERATING PULSES OF LINEARLY VARYING PERIOD, Ser. No. 331,575 and the commonly owned application of Willian G. Eppler, Jr., entitled- IMPROVED SPEECH COMPRESSOR- EXPANDER WITH SIGNAL SAMPLE ZERO RE- SET, Ser. No. 331,536 filed of even date herewith.

BACKGROUND OF THE INVENTION This invention relates generally to sound or speech compressors in which a sound recording is reproduced at a speed different than the speed at which the sound was recorded and the frequency components of the recorded signal are restored to approximate those'of the normal speech which was recorded thus permitting a recording to be played back with normal speech frequencies but at an elapsed time different than that in which the recording was made. If the playback transport is run at a higher speed than the recording speed the time is compressed-and the infonnation is played back in less time than was taken to record it. If the transport is run at a slower speed than its recording speed the time is expended and the information conveyed in a longer time than it took to record. In this application, compression will be used generically to mean both time compression and time expansion hence the compression ratio, C, is greater than one for time compression and a value between zero and less than one for time expansion.

SUMMARY OF THE INVENTION The present invention provides in a speech compressor-expander an improved ramp generator for controlling a voltage controlled period generator to generate a linearly-varying-periodicity square wave for controlling the shift period of analog shift registers through which the time-compressed sound signal passes for frequency restoration. The motor speed control and the ramp generator are controlled from a single manual control to select the compression ratio thereby coordinating the speed at which the transport motor runs with the selection of the ramp slope to ultimately control the rate of change of the linear period variation of the square wave generator thus providing the desired frequency transformation for restoring the normal frequency spectrum of the sound or. speech signals. In passing the signal through the analog shift registers the delay registers are separated into two equal sections and the signal is shifted through the two halves of the analog shift register with a signal inversion imposed for the signals which pass through one-half of the register. The signals are combined from the outputs of the two halves of the register either arranged serially or in parallel and in either event the processing disturbance component introduced by applying the linearly varying square wave as the shift period for the registers is cancelled by the inversion technique whereas the sound signal components are additive thereby improving .the signal level and greatly, decreasing the processing noise component level. At theend of the periodic'variation of the analog shift registers the present invention provides improved zero crossingdetection for the signal and operates to blank the audio output during reset of the ramp and control period generators during discard of the signal stored therein and the period it takes to reload the register prior to outputsignal once again appearing at the output terminals thereof. In addition, the present invention provides an improved control of the repetitive sample period to optimize the relation of sample and discard time with the characteristics of human speech and the selected compression ratio.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram partly pictorial of an overall speech compression system according to the invention.

FIG. 2 is an overall block diagram partly schematic of a signal processor and control circuits thereforin accordance with the invention.

FIG. 2A is a schematic diagram of the voltage controlled period generator.

FIG. 2B is a waveform diagram useful for explaining the operation of FIG. 2A.

FIG. 3 is a waveform diagram of the blank enable and blank gating control of the output.

FIG. 4A isa schematic diagram of the blank enable and automatic reset circuit.

FIG. 4B is a diagram of the ramp generation operation with varying period for compression.

FIG. 4C is a diagram of the ramp generation opera tion with approximately constant period for expansion.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, a self-contained tape playback unit incorporating speech compression features in accordance with theinvention is shown. The unit comprises the usual record storage and transport system for relatively moving a sound record past the transducer to obtain an electrical signal representative of the recorded sound. As shown in FIG. 1 a pair of reels 11 and 12 contain a magnetic tape recording 13 which is drawn past a playback head 14 when the reels l1 and 12 are rotated with or without a capstan drive for the tape as is known in the art and the transducer in playback head 14 produces on line 15 an electrical signal representing the sound recorded on the tape 13. The frequency spectrum of the electrical signal on line 15 will be determined by the speed at which the tape 13 is moved past the transducer in the playback head'14 and for this purpose the drive of the reels 11, 12 and/or the capstan on the tape 13 is controlled by a variable speed motor 16. The speed is selected by manual control 17 which can be set for a range of speeds which includes speeds equal to, greater than, and less than the speed at which the sound recording was initially impressed on the tape 13.

The signal on line 15 passes through a preamplifier equalizer 21 which may have automatic volume control and otherwise is adapted to condition the signal and compensate for the frequency response involved in the magnetic recording and transducing system and produce a relatively constant amplitude audio analog signal on line 22 representing the sound signal. The signal on line 22 is passed through a frequency conversion processor 23 which operates under the control of a control circuit 24 to convert the frequency spectrum of the signals on line 22 into normal range speech frequency signals on line 25. The features of the circuits 23 and 24 are described in detail hereinafter.

The frequency restored signal on line 25 is amplified for audio reproduction in an amplifier 26 which may have the usual volume control 27 and tone control 28 and is further subject to a blanking control 29 to produce an output signal on line 31 which is transduced into an audible reproduction by the audio transducer 32. In order to coordinate the operation of the device to provide frequency transformation corresponding to that required by the speed selected for the motor 16, the manual control 17 also is coupled as indicated at 33 to control the operation of control circuit 24 and frequency processor 23 to obtain the desired frequency restoration of the signals being processed through unit 23.

Referring now to FIG. 2 the general arrangement of the frequency processor 23 and control circuit 24 will be described.

Manual control 17 selects motor speed by means of control circuit 44. The motor control circuit 44 also provides an output signal in accordance with the setting of C which is applied to an f(c) circuit 45 which transforms the linear setting of C on control 17 to a voltage on line 41 which includes the function K (C l)/(C l) as the functional relation for establishing the ramp slope as a function of compression factor C. This input on line 41 to ramp generator 42 produces on output line 46 a ramp voltage which has a predetermined slope and repetition interval determined by the input voltage on line 41. The ramp generator 42 resets from signal on line 53 and the slope of the ramp is determined by the input signal on line 41. The basic period of the ramp will decrease as the slope increases for compression ratios of C greater than one as hereinafter described.

The V voltage on line 41 is applied on line 47 to a blank enable circuit 43 which determineswhether the unit is in compression or expansion mode by sensing the voltage on line 47 relative to a fixed level such as 7.8 volts. When the voltage on line 47 is above 7.8 volts the unit is compressing speech for C greater than one end for this condition the blank enable circuit 43 will produce two outputs as the ramp excursion approaches its end value of 2.0 volts. By sensing an input on line 48, from the output of ramp generator 42 on line 46, the blank enable circuit 43 produces on line 49 a blank enable signal when the input on line 48 crosses the three volt level and produces a reset signal on line 51, when the signal on line 48 reaches the two volt level which is the designated end of the ramp period. If the end of the ramp period is reached by the ramp voltage reaching the two volt level, the reset pulse on line 51 will trigger a one shot 52 which is connected on line 53 to reset the ramp generator 42 and at the end of the reset one shot pulse which resets the ramp generator 42 to 7.8 volts the next ramp excursion begins. The length of the reset one shot pulse from unit 52 is long enough to permit the ramp generator to reset to 7.8 volts as a starting oint.

p The output V of the ramp generator 42 is applied to a voltage controlled period generator 54 which generates on line 55 a square wave output which has a pulse period that varies linearly with the linear variation of the ramp voltage V One form of the voltage controlled period generator 54 is shown in FIG. 2A to comprise a current generator 56 generating current I and a current generator 57 generating selectively a current 21 in the opposite direction both currents being used to charge and discharge a capacitor 58. The current I, through generator 56 flows continuously and the current 2I through generator 57 flows in the opposite direction selectively to establish the voltage across capacitor 58. Control of the generator 57 is in accordance with the function V established as an on and off signal from the output 60 of a flip-flop 59. The state of the flip-flop 59 is established by the outputs of two voltage comparators 61 and 62 which each have as inputs the voltage V from capacitor 58. For comparator 61 the other input is a voltage E which is at a fixed predetermined level. For the other input of comparator 62 the input voltage V from the ramp generator 42 is applied. The fixed voltage E is always greater than the input voltage V The operation of the circuit of FIG. 2A can be explained with reference to the diagram of FIG. 23 where the constant voltage E is indicated and the discharge current I, causes the voltage on capacitor 58-to fall at a constant rate indicated at 63 until the voltage level V is reached whereupon the output V turns the current from generator 57 on and current 2h chargescapacitor 58 along the straight line charging path 64. The slopes 63 and 64 are equal and opposite since the discharge rate I is cancelled and exactly equalled in the opposite direction by the charging current 2I As soon as the excursion 64 reaches the voltage level E the flip-flop 59 changes state removing V as control voltage to interrupt the generation of 2I in current generator 57. The process repeats as indicated in FIG. 2B and with the input voltage V having a linear variation, the period of the control waveform V will be as indicated, a series of square waves having a period linearly increasing with time. This output V is applied on line 55 as the output of the voltage controlled period generator 54. Typically the shift period may vary for the 256 shift stages of storage delay herein disclosed between 4p.s and 62.5us.

For expansion the waveforms in FIG. 25 would be modified in that the slope of V0 would be positive and start at the minimum value for Vp. These conditions in the circuit of FIG. 2A would generate an output pulse waveform V with pulses of initial maximum width and pulse period linearly decreasing with time between the end points previously described.

The output on line 55 is applied to a phase splitting driver circuit 65 which produces on outputs 66 and 67 phase opposed square waves corresponding to the square wave input on line 55 which are the (in, 42 drives for shifting analog signals through a pair of 256 storage stage analog shift registers 68 and 69.

The shift registers 68 and 69 are connected for processing disturbance cancellation introduced by the operation of the units at a varying shift pulse period. For this purpose the audio signal on line 22 from preamplifier 21 in FIG. 1 appears at input terminal 71 of an amplifier 72 which has its output connected asan input to analog sift register 68 and also connected to an inverter 73. The output of the inverter 73 is applied as the input signal for analog shift register 69. The outputs of the shift registers 68 and 69 are applied as the subtractive inputs to a differential unit gain amplifier at the input of an audio amplifier unit 74.

The just described circuit including the shift registers 68 and 69 and the amplifier 71 and an inverter 72, together with the differential input amplifier 74 provides for frequency transformation of the input signal on line 71 and at the same time cancellation of the disturbances and distortion introduced by processing that signal through the shift register 68 and 69. Further detailed description of this circuit and related circuits which can be used for the same purpose will be found in applicants copending application entitled SYSTEM FOR NULLIFYING SIGNAL PROCESSOR DISTOR- TIONS Ser. No. 33 1,576 filed of even date herewith.

The amplifier 74 further amplifies the difference signal obtained by combining the two inputs from the shift registers 68, 69 and supplies the amplified audio output signal on line 25. Also contained in the unit 74 is a zero crossing detector which provides on output line 75 a.

series of pulses representing the time of detection of zero crossings of the differenced input signal.

A blank-unblank control circuit 76 receives the zero crossing pulses on line 75 and operates when enabled by the blank enable signal on line 49 to produce an output-blanking signal on line 77 which blanks the output of audio amplifier 74. Tis arrangement permits the output signal level on line 25 to be blanked to zero signal level during the reset period for the shift registers and ramp generator controlled portions of the circuit. The circuit 76 is responsive to a signal on line 78 to tenninate the blanking output on line 77 thereby permitting the signal on output line 25 to resume its signal level value.

A counter 81 produces an output on line 78 at the end of 256 counts corresponding to the length of the individual registers 68, 69 responsive to the pulses from line 55 applied on the counter input 82. When the counter 81 completes a count of 256 input pulses on line 82 it produces an output on line 78 that ends the blanking period pulse on line 77. A similar output to that on line 53 appearing on line 83 resets the counter 81. The interval timed by the counter 81 counting 256 counts of the pulse signal on line 55 provides blanking duration for the amplifier 74 sufficient to permit the pulses on line 55 after passing through drivers 65 to shift the registers 68, 69 and empty the contents thereof before unblanking occurs and audio output on line 25 is resumed. At the same time the shift pulses are applied to the registers 68, 69 to enter audio signal from terminal 71 through the amplifier and inverter 72, 73, so that the registers 68, 69 are full at the end of the blanking interval and ready to supply audio samples to the input of amplifier 74 and resume the next signal period.

In the event that no zero-crossing signal on line 75 occurs during the enabled period established by the signal on line 49 prior to the occurrence of the reset signal on line 51, then the reset signal which is applied on line 83 to the counter 81 immediately causes a blank output signal on line 78 to the circuit 76 to blank the audio amplifier 74 by appropriate signal on line 77. Again, the action of the counter 81 removes the signal on line 78 to remove the blanking signal on line 77 at the end of the count of 256 pulses on input line 82. The audio output is this blanked for the duration of the output pulse from reset one shot 52 plus the period required to count 256 counts in counter 81 plus the interval of time after the end of the 256 count for the detection of the next signal zero-crossing. The blank-unblank control logic 76 comprises a D flip-flop and with the inputs indicated on lines 49, and 78 the control of the output will be as indicated in FIG. 3. The enable input 49 permits blanking upon the occurrence of a zero crossing within the enable interval, and if it does not occur then the reset one shot pulse on 83 forces'the start of the blank interval by signal on line 78 which continues during the 256 counts in the counter 81 At the end of the 256 counts the signal on line 78 permits removal of the blanking signal at the occurrence of the next zerocrossing detection signal on line 75 causing it to switch the output on line 77.

For time expansion, i.e., when C is less than one, the voltage signal on line 47 as applied to the blank enable unit 43 is compared with the E voltage on line 50, shown as 7.8 volts, to generate a ramp of opposite slope and substantially constant repetition interval in the ramp generator 42. Also a blank enable signal on line 49 as the ramp approaches its end value of 7.8 volts and the end reset pulse on line 51 are produced as herein described.

Referring now to FIG. 4A a detailed description of the construction of the ramp generator 42, blank enable unit 43 and reset one shot 52 and their interrelation will be given. In FIG. 4A the portion to the left of the dashed line generally relates to the ramp generator 42 shown in FIG. 2 and the portion in FIG. 4A to the right of the dashed line generally relates to the units 43 and 52in FIG. 2. The ramp generator 42 comprises essentially a voltage capacitor 91 supplied by a constant current source 92 and a variable current source 93. The current from the source 92 charges capacitor 91 and the current through source 93 discharges capacitor 91. The current generator 93 is voltage controlled by the voltage V on line 47 such that when the signal V is equal to the value E the current discharge rate through source 93 is equal to the current charging rate from source 92 and no voltage change occurs across the capacitor 91. For other values of the voltage V the current drawn by source 93 will be either greater than or less than the current supplied by source 92 and a corresponding change in the voltage across the capacitor 91 will occur. Thus the voltage across capacitor 91 will be either a positive or negative slope ramp with the sign of the slope determined by the relative magnitudes of V and E and the value of the slope determined by the difference in their magnitudes. This ramp voltage appears as an output on line 46 for supplying the input to voltage controlled period generator 54 as previously described.

For time compression the value of C will be greater than 1 and the voltage V will be greater than the voltage E and have a value determined by the selected value of compression ratio C and the voltage analog of that setting produced by motor control circuit 44 as modified by function circuit 45.

For controlling the ramp generation a series of voltage comparators 94, 95, 96, 97 and 98 are provided. The characteristic of the comparators 94-98 is to provide a ONE output if the plus input is greater than the minus input and a ZERO output for the opposite condition. Comparators 94, 95 and 96 have the ramp voltage across the capacitor 91 applied to the negative inputs thereof and this same voltage is applied to the positive input of comparator 98. The voltage E on line 50 is applied to the positive input of comparator 97 and to the negative input of comparator 98. The voltage V EC is applied to the negative input of comparator 97 and a voltage between V and the voltage E is applied to the positive input of comparator 96 by means of the voltage divider connecting lines 47 and 50 with the positive input to comparator 96 connected to the junction thereof. Comparator 94 has a +2 volt input to its positive terminal and comparator 95 has a +3 volt input to its positive terminal. The outputs of the comparators 94-98 are NAND connected to provide the blank enable signal on line 49 and the reset pulse on line 51 as follows: Blank enable signal on line 49 is derived from NAND 105 which receives inputs from the output of comparator 96 and a NAND 106. The NAND 106 receives inputs from the output of comparator 95 and from an inverter 107 which has as its input the output of comparator 97.

The reset pulse on line 51 is derived from the output of a NAND 108 the inputs of which are derived from the outputs of NANDS 109 and 110. The inputs to NAND 109 are derived from the output of inverter 107 and the output of comparator 94. The inputs to NAND 110 come from the outputs of comparators 97 and 98.

The reset pulse on line 51 triggers reset one shot 52 to produce the reset pulse on line 53 which controls a gate 111 enabling it to pass signal from a buffer amplifier 112 when enabled. The output of the gate 111 passes the output from amplifier 112 to establish the reset voltage level for capacitor 91 during reset. The voltage to which capacitor 91 will be reset is determined by the relative magnitude of V and E. When V is greater than E the voltage input to amplifier 112 is derived from line 50 at the potential of E through resistor 113 and thus for compression ratios greater than one the reset is to a constant voltage level B. When V is less than E a diode 114 is poled to conduct and the input to amplifier 112 corresponds to the potential V and the capacitor 91 will be charged to the variable voltage level established by V on line 47.

The operation of the circuit of FIG. 4A for time compression when C is greater than one will now be described with reference to FIG. 4B waveforms. The voltage V is greater than the voltage E thereby making comparator 97 have a zero output and disabling the NAND 110. Thus the output of 98 does not effect the production of reset signal on line 51. The output of inverter 107 is a one enabling NAND 109 thereby allowing comparator 94 to control the generation of reset pulse on line 51 when the voltage on capacitor 91 drops below the +2 volt level on the input of comparator 94. The output of inverter 107 at this time also has enabled the NAND 106 and thus the output of comparator 95 controls NAND 105 to produce blank enable pulse on line 49 when the voltage on capacitor 91 drops below the +3 volt level. The output of NAND 96 is a one since voltage E is greater than the voltage at capacitor 91 for all values of V greater than E. Thus the charging rate for capacitor 91 is varied by the voltage V but the reset and blank enable signals are generated at a constant voltage level of two and three volts as shown in FIG. 413 with the resultant variation in repetition period for the ramp voltage as it falls from 7.8 volts to three and two volt levels at the various slopes determined by Vhd EC. For very small compression ratios greater than one the period would be very long and gradually reduce to approximately 30ms for C=2 and 20ms for C=3 as typical values. Since V establishes the ramp slope as proportional to C l)/(C l), the period for C l is approximately proportional to (C l )/(C 1 For C=l, V is equal to E and the charge and discharge current for capacitor 91 will be equal. The voltage thereacross is constant thuseffectively providing a zero slope ramp or fixed delay and no frequency conversion through the analog shift registers.

For the compression ratio C being less than one, V is less than E, and the output of comparator 97 is a one enabling NAND to permit the output of comparator 98 to control generation of the reset signal on line 51. The output of inverter 107 is a zero thus disabling NANDS 106 and 109. For the condition of voltage across capacitor 91 becoming greater than E-R (EV where the constant R might be approximately equal to 0.1 as determined by the voltage divider to which the positive input of comparator 96 is connected, the output of 96 becomes a zero and a blank enable output is produced on line 49 from NAND 105. When voltage 91 reaches the end of the ramp at E the output of comparator 98 becomes a one to produce a reset pulse on line 51 through NANDS 110 and 108. This action is shown in FIG. 4C where various levels of V are indicated as the starting point for the ramp voltage rise to the voltage E at 7.8 volts. The quantity ER(EV varies somewhat with the value of V making the blank enable point on the ramp vary (shown exaggerated in FIG. 4C) but keeping the period of the ramp approximately constant. A typical repetion period for the system shown would be 40-50ms.

Many modifications will now occur to those skilled in the art particularly in view of the broad features of applicants copending applications. In particular although the present disclosure is specific to one analog shift register as the delay line medium, various other forms of controlled delay elements used singly or in combination controlled alternately or otherwise are to be considered as within the scope of the invention as defined by the appended claims:

I claim:

1. A sound reproducer for playing recordings at different reproduction speeds comprising:

a transport for moving said recording relative to a transducer for producing an electrical signal of the sound record on said recording with a frequency spectrum for said electrical signal related by a factor determined by the speed of said transport to the frequency spectrum of said sound recorded as said sound record;

a controllable speed drive for said transport;

analog shift register means having signal input and output terminals'and a shift signal input;

signal means for coupling said electrical signal from said transducer to said input terminal;

a controllable pulse period square wave generator coupled to said shift signal input to shift signals through said analog shift register with the period of said generator;

a ramp control signal generator having means for selecting the sign and slope value for an output ramp control signal to produce repetitive linear variation of said ramp control signal over a range of variation and for resetting to predetermined initial value at the end of said variation;

means coupling said output ramp control signal to control said square wave generator for producing successive repetitive variation of the period of said square wave generator with selected sign and rate of change; output means coupled to said output terminal to receive the signals shifted through said analog shift register and operative for utilizing only successive signal portions shifted to said output terminal during said successive repetitive variation of said period of said square wave;

manually operable control means for selecting said factor by selecting the speed of said transport to be greater than, equal to, or less than the transport speed at which said sound was recorded on said record; and

means responsive to said manually operable control means for relating said selected sign and rate of change of said variation of said period to said factor to restore the frequency spectrum of said signal portions to that of said sound recorded on said sound record.

2. Apparatus according to claim I and including means for decreasing the repetition interval for said repetitive variation directly as the speed of said transport is selected to be greater than the speed at which said sound was recorded.

3. Apparatus according to claim 1 in which said analog shift register means comprises two equal length analog shift registers, and said signal coupling means couples said electrical signal to the input of one of said analog shift registers inverted relative to the input to the other register and means for combining the outputs of said registers to add the signal components and cancel the noise characteristics of said registers in said output means.

4. Apparatus according to claim 1 in which said output means includes:

blanking means operable for blanking the signal level between said successive signal portions;

enabling means operative near the end of said repetitive linear variation of said ramp control signal for enabling said blanking means;

zero crossing signal detector means for detecting zero crossings of signals coupled to said output means; and

circuit means responsive to a detected zero crossing during the period of said enabling for operating said blanking means for a predetermined interval between said successive signal portions.

5. Apparatus according to claim 4 including means operable for terminating said predetermined interval in response to detection of a zero crossing after resetting of said linear variation to said initial value.

6. A sound reproducer for playing a sound record at playback speed different than its recorded speed comprising means for transporting said sound record at a selected playback speed relative to a transducer to obtain an electric signal having frequency components altered by the ratio of said playback speed to said recorded speed;

means for frequency converting said electric signal with a repetitive varying time delay function having time delay variation adjusted in response to selection of said playback speed to be proportional to (C l)/(C l) where C is said ratio of said playback speed to recorded speed; and

means responsive to adjusting said delay variation for varying the repetitive interval of variation for said delay function approximately in direct relation to (C+ l)/(C- l) forC 1.

7. Apparatus according'to claim 6 in which said repetitive interval of variation is approximately 10 (C 1)/(C 1) milliseconds. Y

8. Apparatus according to claim 6 in which said repetitive interval of variation is maintained substantially constant for C l.

9. Apparatus according to claim 7 in which said repetitive interval of variation is maintained substantially constant for C l.

10. Apparatus according to claim 9 in which said repetitive interval of variation for C l is approximately 50 milliseconds.

11. In speech signal processing in which frequency transformation of speech signals to restore their normal frequency spectrum is achieved by passing the signals through analog shift register means which is controlled with a repetitive variation of the shift period, the improvement which comprises providing said analog shift register means as at least two equal length registers, inverting the signal portion in one of said registers relative to the signal in the other register and combining the outputs from said two registers additively as to signals passedthrough said shift registers and subtractively as to characteristics imposed on said signals by operation of said registers.

12. A'sound reproducer for playing a sound record at playback speed different than its recorded speed comprising:

means for transporting said sound record at a selected playback speed relative to a transducer to obtain an electric signal having frequency components altered by the ratio of said playback speed to said recorded speed; and

means for frequency converting said electric signal with a repetitive varying time delay function having time delay variation adjusted in response to selection of said playback speed to be proportional to (C l)/(C l) where C is said ratio of playback speed to recorded speed and has a range of values includes: C l, C=l and C 1.

13. In a speed compression-expansion system having variable delay line means repetitively varied to provide frequency transformation of signals passing through the line the combination comprising:

means for sensing zero crossing points on said signal at the output of said line;

enabling means for establishing an interval at the end of each repetitive variation; and

blanking means responsive to detection of a zero crossing within said interval and if no such zero crossing is detected responsive to the end of said interval for blanking signals derived from the output of said line until after the start of the next repetitive variation of said line.

14. Apparatus according to claim 13 in which said blanking means is responsive to the detection of a zero crossing after the start of said next repetitive variation of said line for terminating said blanking.

15. Apparatus according to claim 14 in which said delay line means comprises an analog shift register with controlled shift period and including means for delaying said start of said next repetitive variation at least as long as it takes to shift said analog shift register to be filled from the input signals applied thereto.

O I UNITED STATES PATENT AND TRADEMARK OFFICE i CERTIFICATE OF CORRECTION PATENT NO. 3,828,361 DATED August 6, 1974 r i INV ENTOR(S) Murray M. Schiffman It is certified that error appears in the ab0veidentified patent and that said Letters Patent 1 are hereby corrected as shown below: i

. In the legend: [73] Assignees: correct the name of v 1 Murray M. Schiffmam" to Murray M. Schiffman Change "Attorney, Agent, or Firm Chittick, Thompson & Pfund" 1 to Attorney, Agent, or Firm Dike, Bronstein, Roberts, Cushman & Pfund Column 1, line 34 "expended" should be expanded -:v y

line 15 "Willian" should be William Column 3, line 49, "end' should be and Column 4, line 64, "sift" should be shift Column 5, line 26, "Tis" should be This v line 65, "This" should be Thus Column 7, line 67 "V EC" should be V Q gi d and Scaled this eighteemh D of Novemberl975 [SEAL] Arrest:

N RUTH c. MASON C. MARSHALL DAN .IIH'XIIHX' ()fjnvr ('mnmissrmrcr u! PUH'HIS and Trademark 

1. A sound reproducer for playing recordings at different reproduction speeds comprising: a transport for moving said recording relative to a transducer for producing an electrical signal of the sound record on said recording with a frequency spectrum for said electrical signal related by a factor determined by the speed of said transport to the frequency spectrum of said sound recorded as said sound record; a controllable speed drive for said transport; analog shift register means having signal input and output terminals and a shift signal input; signal means for coupling said electrical signal from said transducer to said input terminal; a controllable pulse period square wave generator coupled to said shift signal input to shift signals through said analog shift register with the period of said generator; a ramp control signal generator having means for selecting the sign and slope value for an output ramp control signal to produce repetitive linear variation of said ramp control signal over a range of variation and for resetting to predetermined initial value at the end of said variation; means coupling said output ramp control signal to control said square wave generator for producing successive repetitive variation of the period of said square wave generator with selected sign and rate of change; output means coupled to said output terminal to receive the signals shifted through said analog shift register and operative for utilizing only successive signal portions shifted to said output terminal during said successive repetitive variation of said period of said square wave; manually operable control means for selecting said factor by selecting the speed of said transport to be greater than, equal to, or less than the transport speed at which said sound was recorded on said record; and means responsive to said manually operable control means for relating said selected sign and rate of change of said variation of said period to said factor to restore the frequency spectrum of said signal portions to that of said sound recorded on said sound record.
 2. Apparatus according to claim 1 and including means for decreasing the repetition interval for said repetitive variation directly as the speed of said transport is selected to be greater than the speed at which said sound was recorded.
 3. Apparatus according to claim 1 in which said analog shift register means comprises two equal length analog shift registers, and said signal coupling means couples said electrical signal to the input of one of said analog shift registers inverted relative to the input to the other register and means for combining the outputs of said registers to add the signal components and cancel the noise characteristics of said registers in said output means.
 4. Apparatus according to claim 1 in which said output means includes: blanking means operable for blanking the signal level between said successive signal portions; enabling means operative near the end of said repetitive linear variation of said ramp control signal for enabling said blanking means; zero crossing signal detector means for detecting zero crossings of signals coupled to said output means; and circuit means responsive to a detected zero crossing during the period of said enabling for operating said blanking means for a predetermined interval between said successive signal portions.
 5. Apparatus according to claim 4 including means operable for terminating said predetermined interval in response to detection of a zero crossing after resetting of said linear variation to said initial value.
 6. A sound reproducer for playing a sound record at playback speed different than its recorded speed comprising means for transporting said sound record at a selected playback speed relative to a transducer to obtain an electric signal having frequency components altered by the ratio of said playback speed to said recorded speed; means for frequency converting said electric signal with a repetitive varying time delay function having time delay variation adjusted in response to selection of said playback speed to be proportional to (C - 1)/(C + 1) where C is said ratio of said playback speed to recorded speed; and means responsive to adjusting said delay variation for varying the repetitive interval of variation for said delay function approximately in direct relation to (C + 1)/(C - 1) for C >
 1. 7. Apparatus according to claim 6 in which said repetitive interval of variation is approximately 10 (C + 1)/(C - 1) milliseconds.
 8. Apparatus according to claim 6 in which said repetitive interval of variation is maintained substantially constant for C <
 1. 9. Apparatus according to claim 7 in which said repetitive interval of variation is maintained substantially constant for C <
 1. 10. Apparatus according to claim 9 in which said repetitive interval of variation for C < 1 is approximately 50 milliseconds.
 11. In speech signal processing in which frequency transformation of speech signals to restore their normal frequency spectrum is achieved by passing the signals through analog shift register means which is controlled with a repetitive variation of the shift period, the improvement which comprises providing said analog shift register means as at least two equal length registers, inverting the signal portion in one of said registers relative to the signal in the other register and combining the outputs from said two registers additively as to signals passed through said shift registers and subtractively as to characteristics imposed on said signals by operation of said registers.
 12. A sound reproducer for playing a sound record at playback speed different than its recorded speed comprising: means for transporting said sound record at a selected playback speed relative to a transducer to obtain an electric signal having frequency components altered by the ratio of said playback speed to said recorded speed; and means for frequency converting said electric signal with a repetitive varying time delay function having time delay variation adjusted in response to selection of said playback speed to be proportional to (C - 1)/(C + 1) where C is said ratio of playback speed to recorded speed and has a range of values includes: C<1, C 1 and C>1.
 13. In a speed compression-expansion system having variable delay line means repetitively varied to provide frequency transformation of signals passing through the line the combination comprising: means for sensing zero crossing points on said signal at the output of said line; enabling means for establishing an interval at the end of each repetitive variation; and blanking means responsive to detection of a zero crossing within said Interval and if no such zero crossing is detected responsive to the end of said interval for blanking signals derived from the output of said line until after the start of the next repetitive variation of said line.
 14. Apparatus according to claim 13 in which said blanking means is responsive to the detection of a zero crossing after the start of said next repetitive variation of said line for terminating said blanking.
 15. Apparatus according to claim 14 in which said delay line means comprises an analog shift register with controlled shift period and including means for delaying said start of said next repetitive variation at least as long as it takes to shift said analog shift register to be filled from the input signals applied thereto. 